Method for fabricating a semiconductor device having a metallic silicide layer

ABSTRACT

A protective layer is formed on a metallic layer prior to forming a metallic silicide layer, and the protective layer has a thickness thicker than that of the metallic layer.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claiming priority under 35 U.S.C. § 119to Japanese Application No. 2001-354411 filed on Nov. 20, 2001 which ishereby incorporated by reference in its entirely for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method for fabricating asemiconductor device which has a metallic silicide layer.

[0004] 2. Description of the Related Art

[0005] In a method for fabricating a semiconductor process, a metallicsilicide layer is used for a gate electrode, an active region orconductive line in order to realize lower resistance.

[0006] A self-aligned silicide (SALICIDE) method is well known as amethod for forming the metallic silicide layer. In the SALICIDE method,first a metallic layer, such as refractory metal is formed on a siliconsubstrate, and then plural heat treatments are carried out. Generally, afirst heat treatment is for forming a metallic silicide in a surface ofthe substrate by diffusing a material of the metallic layer into thesubstrate. Other heat treatments are for reducing a resistance of themetallic silicide layer. Thereby, the metallic silicide layer can beformed in predetermined portions in the substrate by a self-alignedmethod.

[0007] Such SALICIDE method is disclosed in Japanese Laid-Open PatentPublication:HEI1O-335261, published on Dec. 18, 1998, Japanese Laid-OpenPatent Publication:2000-82811, published on Mar. 21, 2000, “Sub-QuarterMicron Titanium Salicide Technology With In Situ Silicidation UsingHigh-Temperature Sputtering” NEC Corporation, 1995 Symposium on VLSITechnology Digest of Technology Papers, p.57-58 and “The Orientation ofBlanket W-CVD on the underlayer Ti/TiN studied by XRD” ToshibaCorporation Semiconductor Company, ADMETA2000:Asian Session, PS-'210,p71-72.

[0008] On the other hand, a SOI (Silicon-On-Insulator) structure havinga thin single silicon layer formed on an insulating film on a siliconsubstrate is well known as a structure for realizing lower powerconsumption.

[0009] A technique for applying the SALICIDE method to the SOI structurehas been developing in order to realize both a lower resistance andlower power consumption.

[0010] A single silicon layer of a fully depleted SOI structure is verythin. Generally, a thickness of such single silicon layer is less than50 nm. In the case where a thickness of a metallic layer formed on thesingle silicon layer is 25 nm, a thickness of metallic silicide layersformed in an active region (source and drain regions) becomes 50 nm.That is, the metallic silicide layer in the fully depleted SOI structuremight be contacted with the insulating film under the thin singlesilicon layer without making precisely adjustments to a thickness of themetallic layer formed on the single silicon layer. Such contacted areamakes a contact resistance between the metallic silicide layer and thesingle silicon layer larger since an interface region between themetallic silicide layer and the single silicon layer becomes smaller.Further, in the case where a thickness of the metallic layer is verythicker than that of the single silicon layer, quantity of silicon inthe single silicon region is insufficient for reacting with metal in themetallic layer. As a result, voids occur in the active region due tolack of silicon in the single silicon layer.

[0011] Therefore, in the case where the SALICIDE method is applied forthe SOI structure, a process for forming a thin metallic layer on theactive region for forming a thin metallic silicide layer is required.

[0012] However, thin wire effect is well known in the conventionalsilicide process. That is, the narrower a width of the metallic silicidelayer becomes, the larger a sheet resistance of the metallic silicidelayer becomes. Further, the thin wire effect is remarkable in the thinmetallic silicide layer.

SUMMARY OF THE INVENTION

[0013] In a preferred embodiment of the invention, a protective layer isformed on a metallic layer prior to a step for forming a metallicsilicide layer, and the protective layer has a thickness thicker thanthat of the metallic layer.

[0014] According to the present invention, a semiconductor device havinga thin metallic silicide layer can be formed with reducing a sheetresistance by thin wire effect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0016]FIG. 1-FIG. 5 are partial cross-sectional views describing aconventional method of fabricating a semiconductor device.

[0017]FIG. 6-FIG. 10 are partial cross-sectional views describing amethod of fabricating a semiconductor device according to a preferredembodiment.

[0018]FIG. 11(a)-FIG. 11(c) are partial cross-sectional views describingvarious sputtering methods.

[0019]FIG. 12 is a x-ray diffraction describing a relation betweenorientation of 200) surface and each temperature.

[0020]FIG. 13 is a relation between sheet resistance and width ofsilicide layers according to the preferred embodiment.

[0021]FIG. 14 is a partial cross-sectional view describing a method ofanother preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described hereinafter withreference to the accompanying drawings. The drawings used for thisdescription typically illustrate major characteristic parts in orderthat the present invention will be easily understood. In thisdescription, one embodiment is shown in which the present invention isapplied to a MOS transistor.

[0023] First, an outline of a conventional process is shown in FIGS.1-5. A method for forming a titanium silicide layer is describedhereinafter.

[0024] A gate electrode 11 which is comprised of polycrystalline siliconhaving a thickness of 200 nm, a gate oxide film 9 (a thickness of 10 nm)under the gate electrode 11, side walls 13 which are formed on the sidesof the gate electrode 11 and field insulating layers 7 (a thickness of400 nm) are formed on a semiconductor substrate 101, as shown in FIG. 1.These elements are defined as a base 111.

[0025] Then, an active region (source and drain regions; not shown) areformed by an ion implantation which introduces p type ions or n typeions into the base 111.

[0026] Then, arsenic ions As+are implanted into the base 111 at 3×10¹⁴cm⁻². Thereby, surfaces of the semiconductor substrate 101 becomeamorphous.

[0027] Next, a titanium layer 121 (a thickness of 20 nm) as a metalliclayer is formed on the base 111 by a sputtering method, as shown in FIG.2.

[0028] Then, a first heat treatment is carried out. That is, the base111 on which the titanium layer 121 is formed, is heated to atemperature of 750° C. in an atmosphere of nitrogen, as shown in FIG. 3.Thereby, titanium silicide layers 131, 132, 133 (a thickness of 60 nm)are formed in interface surfaces. The titanium silicide layers 131, 132,133 are respectively formed on the interface surfaces between thetitanium layer 121 and the active regions and the gate electrode 11.Such titanium silicide layers 131, 132, 133 are composed of a Ti—Silayer which has a composition ratio of titanium and silicon that is 1:1or a Ti₂Si layer which includes more titanium than silicon. So,resistance of the titanium silicide layers 131, 132, 133 is high. Thatis, the titanium layers 131, 132, 133 have a crystalline structure ofC49.

[0029] Then, the titanium layer 132 which is not reacted with silicon inthe semiconductor substrate 101 is removed using mixture liquid of anammonia solution and a hydrogen peroxide solution, as shown in FIG. 4.

[0030] Then, a second heat treatment is carried out. That is, thetitanium silicide layers 131, 132, 133 are heated to a temperature of850° C. Thereby, the TiSi layer or the Ti₂Si layer of the titaniumsilicide layers 131, 132, 133 are respectively changed: into TiSi₂layers 141, 142, 143, as shown in FIG. 5. That is, the titanium layers(TiSi₂) 141, 142, 143 have a crystalline structure of C54. Therefore, asresistance of the titanium silicide layers 141, 142, 143 become lowresistance of the gate electrode 11 and the active regions can bereduced.

[0031] Then, an intermediate layer, contact holes and conductive linesare formed on the base for forming MOS transistors.

[0032] Here, an outline of a process of the present invention is shownin FIGS. 6-14.

[0033] In this embodiment, a fully depleted SOI. (Silicon-On-Insulator)structure is used.

[0034] A silicon-on-insulator (SOI) substrate which is comprised of asilicon substrate 1, a silicon oxide layer 3 on the silicon substrate 1and a single silicon layer 5 on the silicon dioxide layer 3, is used forthis preferred embodiment. A gate electrode 11 which is comprised ofpolycrystalline silicon having a thickness of 200 nm, a gate oxide film9 (a thickness of 10 nm) under the gate electrode 11, side walls 13which are formed on the sides of the gate electrode 11 and fieldinsulating layers 7 (a thickness of 100 nm) are formed on the SOIsubstrate, as shown in FIG. 6. Then, an active region (source and drainregions; not shown) are formed by an ion implantation which introduces ptype ions or n type ions into the single silicon layer 5. Then, arsenicions As+are implanted into the single silicon layer 5 at 3×10¹⁴ cm⁻², 30keV. Thereby, surfaces of the single silicon layer 5 become amorphous.

[0035] Next, a titanium layer 21 which has a thickness of 15 nm as ametallic layer is formed on the SOI substrate by a sputtering method, asshown in FIG. 7. A cobalt layer or a nickel layer can be used for themetallic layer instead of the titanium layer.

[0036] A thickness of the titanium layer 21 is set to an appropriatethickness according to a depth of the active region, that is, a depth ofthe single silicon layer 5. In this embodiment, as a depth of the activeregion in the fully depletion type SOI is less than 50 nm, a thicknessof a metallic silicide layer, such as titanium silicide which is formedin the active region is necessary to be less than the depth of theactive region, that is, the single silicon layer. A thickness of themetallic silicide layer becomes 2.5 times of the thickness of themetallic layer, such as the titanium layer. In this embodiment, athickness of titanium layer 21 is set to 15 nm.

[0037] Collimate sputtering method or Long Throw sputtering method isused for forming the titanium layer 21. In these methods, metal from ametallic target can be straightly sputtered to the SOI substrate.

[0038] In the Collimate sputtering method, a collimate plate PC isarranged between a metallic target T and a semiconductor wafer SUB, asshown in FIG. 11(b). Thereby, metallic particles among all sputteredmetallic particles, which have small angle of incidence can be reachedto the semiconductor wafer SUB.

[0039] In the Long Throw method shown in FIG. 11(c), an interval betweena metallic target and a semiconductor wafer SUB is longer that that of ageneral sputtering method shown in FIG. 11(a). In the general sputteringmethod, the interval is set to 60 nm. On the other hand, the interval ofthe Long Throw method is set to 340 nm. Further, a vacuum level of theLong Throw method is higher than that of the general sputtering methodfor enhancing straight-forwardness of the sputtered metallic particles.Metallic particles which have large angle of incidence larger than θ cannot reach to the semiconductor wafer SUB in this Long Throw method. Asan average of free path of the sputtered metallic particles can belonger by the high vacuum level, a scatter of the metallic particle canbe reduced.

[0040] The SOI substrate is kept at a temperature of 300° C. duringforming of the titanium layer 21 by the Collimate or the Long Throwmethod.

[0041] Here, a x-ray diffraction of the titanium layer formed on thesubstrate which is kept at temperatures of 200° C., 300° C., 400° C. anda room temperature (25° C.) using the Long Throw sputtering method, isshown in FIG. 12. Referring to FIG. 12, under a temperature of 300° C.,the higher a temperature of the substrate is, the stronger anorientation of (200) surface of the titanium layer becomes. Anorientation of (200) surface is weak at a temperature of 400° C.Therefore, a crystalline structure of a titanium layer which is formedat a temperature between 200° C. and 400° C., differs from a crystallinestructure which is formed at under 200° C. or over 400° C.

[0042] Returning to FIG. 7, a titanium nitride layer 23 having athickness of 30 nm is formed on the titanium layer 21, which iscontinuous with forming the titanium layer 21 without exposing the SOIsubstrate to the air. The titanium layer 21 and the titanium nitridelayer 23 are preferred to form successively in the same process chamber.

[0043] As the titanium nitride 23 is successively formed on the titaniumlayer 21 as a protective layer, the titanium layer 21 is protected froman oxidation. That is, the titanium layer which is easy to be oxidized,can be protected against a fall of quality of the titanium layer due tothe oxidation. As a result, the titanium nitride layer 23 has a functionof isolating the titanium layer 21 from an external oxide atmosphere. Atungsten layer can be used for the protective layer instead of thetitanium nitride layer.

[0044] In this embodiment, a thickness of the protective layer, such asthe titanium nitride layer 23 is thicker than that of the metalliclayer, such as the titanium layer 21, for protecting the metallic layerfrom the oxidation. Further, the protective layer is preferred to have athickness more than 30 nm for restraining from incursion of externaloxygen.

[0045] Then, a first heat treatment is carried out. That is, the SOIsubstrate on which the titanium layer 21 and the titanium nitride layer23 are formed, is heated to a temperature of 750° C. in an atmosphere ofnitrogen. Thereby, titanium silicide layers 31, 32, 33 which have athickness of 30 nm respectively are formed in interface surfaces, asshown in FIG. 8. The titanium silicide layers 31, 32, 33 arerespectively formed on the interface surfaces between the titanium layer21 and the active regions and the gate electrode 11. Such titaniumsilicide layers 31, 32, 33 are composed of a Ti—Si layer which has acomposition ratio of titanium and silicon that is 1:1 or a Ti₂Si layerwhich includes more titanium than silicon. So, resistance of thetitanium silicide layers 31, 32, 33 is high. That is, the titaniumlayers 31, 32, 33 have a crystalline structure of C49.

[0046] Then, the titanium nitride layer 23 and the titanium layer 32which is not reacted with silicon in the single silicon layer 5 or thegate electrode 11, is removed using mixture liquid of an ammonia'solution and a hydrogen peroxide solution, as shown in FIG. 9.

[0047] Then, a second heat treatment is carried out. That is, thetitanium silicide layers 31, 32, 33 are heated to a temperature of 850°C. Thereby, the TiSi layer or the Ti₂Si layer of the titanium silicidelayers 31, 32, 33 are respectively changed into TiSi₂ layers 41, 42, 43,as shown in FIG. 10. That is, the titaniumu layers (TiSi₂) 41, 42, 43have a crystalline structure of C54. Therefore, as resistance of thetitanium silicide layers 41, 42, 43 become low, resistance of the gateelectrode 11 and the active regions can be reduced. As thickness of thetitanium silicide layers 42, 43 which are formed in the active region(the source and drain regions) is 30 nm, portions of the titaniumsilicide layers 42, 43 do not reach to the silicon oxide layer 3.

[0048] Then, an intermediate layer, contact holes and conductive linesare formed on the base for forming MOS transistors.

[0049] Although the titanium silicide layers of the preferred embodimentare very thin (30 nm), the titanium silicide layers 41, 42, 43 have lowregular sheet resistance of about 10 Ω/sq, as shown in FIG. 13. Further,the sheet resistance of this embodiment is independent of width oftitanium silicide layer.

[0050] In FIG. 13, black circles denote a relation between width ofsilicide layer and sheet resistance of the preferred embodiment.Further, white triangles denote a similar relation of the conventionalsilicide layer which has a thickness of 30 nm.

[0051] According to the present invention, a SALICIDE method for formingmetallic silicide layers can be applied to a semiconductor substratewhich has a thin silicon layer such as a SOI substrate. Particularly, ina fully depleted SOI structure which has a very thin single siliconlayer, metallic silicide layers can be formed precisely.

[0052] As a result, according to the present invention, a semiconductordevice having a thin metallic silicide layer can be formed with reducinga sheet resistance by thin wire effect.

[0053] In the above embodiment, argon ions can be implanted into the SOIsubstrate instead of the arsenic ions, as shown in FIG. 14. Such argonions Ar+are implanted into the single silicon layer 5 at 5×10¹⁴ cm⁻², 15keV. Thereby, surfaces of the single silicon layer 5 become amorphous.As the implanted argon ions in the substrate are not neither a p typeimpurity nor n type impurity, the argon ions have no serious effect inthe active region in which p channel or n channel type transistors areformed. As a result, the transistors can be precisely formed in theactive region.

[0054] The present invention has been described above with reference toillustrative embodiments. However, this description must not beconsidered to be confined only to the embodiments illustrated. Variousmodifications and changes of these illustrative embodiments and theother embodiments of the present invention will become apparent to oneskilled in the art from reference to the description of the presentinvention. It is therefore contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

What is claimed is:
 1. A method for fabricating a semiconductor device, comprising: preparing a substrate having a silicon region; causing the silicon region to be amorphous by an ion implantation; heating the substrate having the amorphous silicon region at a predetermined temperature; forming a metallic layer on the amorphous silicon region, wherein the metallic layer has a first thickness; forming a protective layer on the metallic layer, wherein the protective layer protects the metallic layer from a surround atmosphere, wherein the protective layer has a second thickness thicker than the first thickness; forming a metallic silicide layer in an interface between the amorphous silicon region and the metallic layer by a heat treatment, wherein the metallic silicide layer is comprised of metal in the metallic layer and silicon in the amorphous silicon region.
 2. The method according to claim 1, wherein argon ions are implanted into the silicon region by the ion implantation.
 3. The method according to claim 1, wherein the predetermined temperature is a temperature of from 200° C. to 400° C.
 4. The method according to claim. 1, wherein the metallic layer is formed on the amorphous silicon region by a long throw sputtering method or a collimate sputtering method.
 5. The method according to claim 1, wherein the metallic layer is comprised of titanium, cobalt or nickel.
 6. The method according to claim 1, wherein a depth of the silicon region is larger than the first thickness of the metallic layer.
 7. The method according to claim 1, wherein the protective layer is comprised of titanium-nitride or tungsten.
 8. The method according to claim 1, wherein the first thickness of the metallic layer is equal to or less than 15 nm.
 9. The method according to claim 1, wherein the second thickness of the protective layer is equal to or more than 30 nm.
 10. The method according to claim 1, wherein a source region and a drain region of a MOS transistor are formed in the silicon region, wherein the metallic silicide layer is formed in the source and drain regions.
 11. The method according to claim 1, wherein the substrate has a silicon on insulator structure which has a single silicon layer formed on an insulating film.
 12. A method for fabricating a semiconductor device, comprising: preparing a SOI substrate having a single silicon region formed on an insulating film; heating the SOI substrate at a temperature of from 200° C. to 400° C.; forming a metallic layer on the single silicon region of the SOI substrate; forming a protective layer on the metallic layer, wherein the protective layer protects the metallic layer from a surround atmosphere; forming a metallic silicide layer in a surface of the silicon region by a heat treatment, wherein the metallic silicide layer is comprised of metal in the metallic layer and silicon in the amorphous silicon region.
 13. The method according to claim 12, wherein the metallic layer has a first thickness, wherein the protective layer has a second thickness which is more than the first thickness of the metallic layer.
 14. The method according to claim 12, wherein argon ions are implanted into the silicon region by an ion implantation before the step of heating the SOI substrate so as to form an amorphous silicon region in the silicon region.
 15. The method according to claim 14, wherein the metallic layer is formed on the amorphous silicon region by a long throw sputtering method or a collimate sputtering method.
 16. The method according to claim 15, wherein the metallic layer is comprised of titanium, cobalt or nickel.
 17. The method according to claim 16, wherein the protective layer is comprised of titanium-nitride or tungsten.
 18. The method according to claim 13, wherein a depth of the silicon region is larger than the first thickness of the metallic layer.
 19. The method according to claim 13, wherein the first thickness of the metallic layer is equal to or less than 15 nm.
 20. The method according to claim 19, wherein the second thickness of the protective layer is equal to or more than 30 nm. 